Fangzhou Ye

Fangzhou Ye

About me

My name is Fangzhou Ye. I am currently a fourth-year PhD Candidate in the Department of Electrical and Computer Engineering at the University of Central Florida, working under the supervision of Dr. Hao Zheng. Prior to my doctoral studies, I earned my Bachelor’s degree in Electronic Science and Technology from Zhejiang University in Hangzhou, China.

My research interests lie at the intersection of Computer Architecture, Machine Learning, and hardware/software co-design for efficient AI. I focus on improving the computational and memory efficiency of modern AI systems through innovations across algorithms, architectures, and system designs. In particular, my work explores sparsity acceleration, with an emphasis on irregular and unstructured sparsity. Moving forward, I aim to further investigate the intersection of large language models (LLMs), retrieval systems, and sparsity, with a focus on developing efficient architectures and systems for emerging AI workloads.

Education

  • 08/2023 – Now: Ph.D. in Computer Engineering, Intelligent Computer Architecture and Technology Laboratory (iCAT), University of Central Florida, Orlando, Florida, USA.
    Thesis Advisor: Dr. Hao Zheng
  • 09/2019 – 07/2023: Bachelor’s in Electronic Science and Technology from Zhejiang University, Hangzhou, Zhejiang, China.

Teaching Experience

  • 01/2025 - 05/2025: EGN 3211 Eng Analysis & Computation, University of Central Florida
  • 01/2025 - 05/2025: EEE 3342 Digital Design, University of Central Florida
  • 08/2024 – 12/2024: EGN 3211 Eng Analysis & Computation, University of Central Florida
  • 08/2024 – 12/2024: EEL 3552 Signal Analysis & Analog Communication, University of Central Florida

Publications

(top-tier conference) is one of the top CS conferences listed on csrankings.org and is also listed as a CCF-A by the China Computer Federation (CCF).

  • Fangzhou Ye, Wei Zhang, Ahmed Louri, Hao Zheng. “MOSAIC: An Accelerator Design for Heterophilic Graph Learning”, in Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO)(Top-tier Conference), Athens, Greece, October 31 – November 4, 2026.
  • Fangzhou Ye, Amir Ghazizadeh Ahsaei, Hao Zheng. “Argus: An Efficient Accelerator Design for Sparse Nonlinear Solver”, in Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO)(Top-tier Conference), Athens, Greece, October 31 – November 4, 2026.
  • Fangzhou Ye, Shilin Tian, Amir Ghazizadeh Ahsaei, Hao Zheng. “TensorPrism: Rethinking Sparse High-order Tensor Acceleration via Co-occurrence Graph”, in Proceedings of the 53rd International Symposium on Computer Architecture (ISCA) (Top-tier Conference), Raleigh, USA, June 27– July 1, 2026.
  • Shilin Tian, Fangzhou Ye, Amir Ghazizadeh Ahsaei, Wei Zhang, Hao Zheng. “PanGaea: A Unified Memory-Efficient Accelerator for Pangenome Chaining and Alignment”, in Proceedings of the 63rd Design Automation Conference (DAC) (Top-tier Conference), Long Beach, CA, July 26-29, 2026.
  • Fangzhou Ye, Lingxiang Yin, and Hao Zheng. “Scaling Graph Neural Network Training via Geometric Optimization”, in Proceedings of IEEE International Symposium on High-Performance Computer Architecture (HPCA) (Top-tier Conference), Sydney, Australia, January 31-February 4, 2026.
  • Amir Ghazizadeh Ahsaei, Lingxiang Yin, Shilin Tian, Fangzhou Ye, Fan Yao, Hao Zheng. “Rethinking Tiling and Dataflow for SpMM Acceleration: A Graph Transformation Framework”, In Proceedings of IEEE/ACM International Symposium on Microarchitecture (MICRO) (Top-tier Conference), Seoul, South Korea, October 18-22, 2025.
  • Fangzhou Ye, Lingxiang Yin, Amir Ghazizadeh Ahsaei, Hao Zheng. “EGMA: Enhancing Data Reuse and Workload Balancing in Message Passing GNN Acceleration via Gram Matrix Optimization”, In Proceedings of the 61st Design Automation Conference (DAC) (Top-tier Conference), San Francisco, CA, June 23-27, 2024.

Patents

  • Shi Binpu, Ye Fangzhou, Liu Shengli, Chen Haoyang, Yu Guanding, “A distributed communication and method”, granted by the China National Intellectual Property Administration (CNIPA), 2023. Patent No. CN115150288B.

Honors and Awards

  • Outstanding Graduate Researcher Award, UCF, 2026.
  • Future Faculty Laureates (FFLs) Program Awards for Doctoral Students, UCF, 2024-2026.
  • Micro Student Travel Grant, MICRO, 2026.
  • ISCA Student Travel Grant, ISCA, 2026.
  • Best Reviewer Certificate, TSUSC, 2025.
  • Micro Student Travel Grant, MICRO, 2025.
  • ORCGS Doctoral Fellowship, UCF, 2023-2024.
  • DAC Young Fellows, DAC, 2024.

Service

Conference Reviewer:

  • DAC 24-26, IPDPS 24, ICCAD 24-26, ISPASS 25-26, MLSys 2026, ICS 2026, HPCA 2027.

Journal Reviewer:

  • IEEE Transactions on Sustainable Computing (TSUSC); IEEE Transactions on Computers (TC); Future Generation Computer Systems; IEEE Transactions on Circuits and Systems I (TCAS-I); IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD); Computing in Springer Nature.

Artifact Evaluation Committee:

  • MICRO’26 Artifact Evaluation PC Member